Various types of circuit arrangements for delaying functional signals are known. For example, delay lines which are formed on a glass substrate and realize a delay of an electrically presented signal by way of the propagation time of acoustic surface waves have since long been known. Other types utilize clocked shift registers for delaying binary useful signals. Also known are types of delay lines in which analog signals in the form of time-discrete signal samples are conducted through so-called bucket brigade circuits in which they are delayed. All delay circuits known thus far have the drawback that they have only one, fixed delay time which is imposed by the construction and which is very difficult or impossible to change during operation. For example, the delay time of a delay line formed by a bucket brigade circuit could be changed by changing the frequency of the clock signal driving the bucket brigade circuit. However, the sampling frequency of the signal samples passing through the bucket brigade circuit is thus also changed in a frequently non-usable manner.
It is an object of the invention to provide a circuit arrangement for delaying a functional signal which can in practice be readily adapted for a plurality of different values of the desired delay time, i.e. a circuit which is preferably switchable.
This object is achieved in accordance with the invention by means of a circuit arrangement for delaying a functional signal which is stored in the form of time-discrete signal samples in a row of storage devices at time intervals determined by a clock signal and is read therefrom after expiration of a selectable delay time, each storage device being connectable, via a respective input circuit, to a functional signal input and, via a respective output circuit, to a functional signal output for this purpose, the input circuit of a storage device being activatable together with the output circuit of the next storage device in the row by a respective activation device, comprising a shift register device formed by a chain of bistable trigger circuits in which the output of each of the trigger circuits is connected to the input of the next trigger circuit in the chain, each activation device comprising one of the trigger circuits and all trigger circuits being switched by the clock signal, and also comprising a command device which applies a (first) start pulse to the first trigger circuit in the shift register device at a first instant and which enables the shift register device to propagate the start pulse through the chain of trigger circuits in conformity with the clock signal and which interrupts the propagation of the (first) start pulse at a second instant and at the same time applies a next start pulse to the first trigger circuit in the shift register device and enables the shift register device again to propose said next start pulse, the time interval between the first instant and the second instant amounting to a selectable, integer multiple of periods of the clock signal the number of storage devices or trigger circuits corresponding at least to said multiple of the periods of the clock signal.
Thus, the circuit arrangement in accordance with the invention is preferably constructed so that a parallel connection of several storage devices for separate, time-discrete signal samples is arranged between the functional signal input for the signal to be deplayed and the functional signal output for the delayed signal. In the recurrency of the clock signal at which the time-discrete signal probes are acquired the storage devices are successively loaded with these signal probes and are read out again after expiration of the desired delay time. The number of storage devices should, therefore, be one greater than the (integer) quotient of the longest desired delay time and the period of the clock signal. In this circuit arrangement the clock signal may remain unchanged even when arbitrary delay times are chosen, so that it need merely be adapted to the requirements imposed in respect of bandwidth on the useful signal transmitted via time-discrete signal samples. A clock signal which is constant and remains unchanged in all signal processing stages can thus be used for complex signal processing with inter alia one or more signal delays.
The possibilities for use of the circuit arrangement in accordance with the invention are also greater than the delay devices having a strictly predetermined delay time. The more flexible circuit arrangement for delaying a functional signal can lead inter alia to simplified circuit concepts in signal processing.
In a preferred embodiment of the invention, the command device comprises a presettable counting device whose counting cycle can be adjusted to the selected multiple of the periods of the clock signal and which outputs one of the start pulses after each counting cycle. This counting device thus enables simple control of the delay time as a selectable multiple of the periods of the clock signal by control signals as used in many complex signal processing devices. This also simply enables program-controlled variations of the desired delay time.
Preferably, the trigger circuits comprise a respective D-flipflop clocked in common by the clock signal, so that the propagation of the start pulse through the shift register device can be controlled in a simple manner. In a further embodiment of the invention, this control is also provided by an AND-gate which precedes the input of each D-flipflop and in which the output signal of the preceding trigger circuit is combined with an enable signal from the command device. The propagation of the start pulses through the shift register device can thus be simply interrupted by a single control signal at any location of the shift register device, i.e. at any instant.
Further embodiments of the invention are recited in the further dependent claims.